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DS2227
NOTES:
1.
WE
is high for a read cycle.
2.
3.
4.
5.
6.
7.
8.
9.
10.
OE = V IH or V IL . If OE = V IH during write cycle, the output buffers remain in a high impedance
state.
t WP is specified as the logical AND of CE and WE .
t DH , t DS are measured from the earlier of CE or WE going high.
t DH is measured from WE going high. If CE is used to terminate the write cycle then t DH = 20 ns.
If the CE low transition occurs simultaneously with or later than the WE low transition, the
output buffers remain in a high impedance state in this period.
If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state in this period.
If the WE is low or the WE low transition occurs prior to or simultaneously with the CE low
transition, the output buffers remain in a high impedance state in this period.
Each DS2227 is marked with a 4-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The minimum expected t DR is defined as starting at the
date of manufacture.
Timings are valid only when CE is tied low.
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns
All Voltages are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL gate
Input Pulse Levels: 0 - 3.0 V
Timing Measurements Reference Levels:
Input - 1.5V
Output - 1.5V
Input Pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
9 of 10
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